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IEEE Test Technology Educational Program 2015 
(TTEP'15)

in conjunction with DATE 2015
March 9-13, 2015
Alpexpo Congress Centre – Grenoble, FRANCE

http://ttep.tttc-events.org/ttep/tutorials.html

http://www.date-conference.com/conference/monday-tutorials

Early registration deadline: Tuesday, February 10, 2015


DATE 2015 - CALL FOR TUTORIALS PARTICIPATION

Scope


TThe Tutorials & Education Group (TEG) of the IEEE Computer Society Test Technology Technical Council (TTTC) organizes in 2015 a comprehensive set of Test Technology Tutorials to be held in conjunction with TTTC sponsored technical meetings.

In this context, the Design, Automation and Test in Europe 2015 (DATE’15) will include 2 excellent TTEP half-day tutorials on high interesting and interdisciplinary technology topic. These tutorials qualify for IEEE TTTC certification and will be presented on Monday, March 9th 2015.
The tutorials require a separate fee and registration.

You can get detailed information on the TTEP website: http://ttep.tttc-events.org/ttep/tutorials.html

Registration


Register for the Tutorials at the DATE 2015 Registration page:

http://www.date-conference.com/registration 

Early registration is approaching: Tuesday, February 10, 2015!

Program


From Data to Actions: Applications of Data Analytics in Semiconductor Manufacturing & Test

Tutorial M09 Testing
March 9, 2015 (Monday)
09:30  - 13:00
Room: Les Bans

Organisers:
Haralampos Stratigopoulos, TIMA Laboratory, FR
Yiorgos Makris, The University of Texas at Dallas, US

Throughout the design and production lifetime of an integrated circuit, a wealth of data is collected for ensuring its robust and reliable operation. Ranging from design-time simulations to process characterization monitors on first silicon, and from high-volume specification tests to diagnostic measurements on chips returned from the field, the information inherent in this data is invaluable. At the same time, the need for cost-effective solutions for various test-related tasks is becoming more pressing, especially in complex mixed-signal Systems-on-Chip. As a result, using data analytics methods to mine this information and identify meaningful correlations has seen intense interest and numerous breakthroughs have been made during the last decade. To motivate the need, the challenges, and the benefits of using data analytics, this tutorial will discuss its utility on the following actual industrial problems: (a) extraction of wafer-level spatial and lot-level spatiotemporal correlation and utilization in test cost reduction, process monitoring, and yield learning, (b) test cost reduction through replacement of costly tests by low-cost alternatives and/or elimination of superfluous tests, either statically or adaptively during test application, and (c) pre-deployment evaluation of candidate test methods through probabilistic test metrics. This tutorial is intended for (a) process and test engineers who wish to understand the utility of data analytics in their practice, (b) graduate students/faculty/researchers who wish to familiarize with the state-of-the-art and conduct research in this domain, and (c) data analytics experts who wish to apply their expertise on semiconductor manufacturing data.

Further information in:
http://www.date-conference.com/conference/tutorial-m09




Memory Test and Reliability in Nano-Era

Tutorial M10 Testing
March 9, 2015 (Monday)
14:30 - 18:00
Room: Les Bans

Chair:
Said Hamdioui, Delft University of Technology, NL

The objective is to provide attendees with an overview of memory test, reliability and yield improvement.

In terms of testing, aspects such as fault modeling, test design and BIST will be covered.  Traditional fault modeling and advanced ones  for current and future technologies are covered. Systematic methods are presented for designing and optimizing tests, supported by industrial results from different companies (e.g. Intel, ST, Infineon) in order to get better insight in the test effectiveness. State-of-the art and novel BIST architectures are covered. Testing of some emerging memories is discussed.

In terms of reliability and yield improvement, effects of process scaling and environment on reliability failures caused by static noise (contributed by crosstalk, IR-drop, threshold voltage variation, negative-bias temperature instability, and random telegraph noise), hot carrier injection (HCI), gate oxide breakdown, latchup, metallization reliability failures and electrostatic discharge/electrical overstress (ESD/EOS) will be discussed. Industry practices for designing for reliability are discussed. Traditional reliability testing approaches such as burn-in, IDDQ/IDD, parametric and at-speed functional testing, and present-day adaptive and data-driven approaches are covered. Self-repair and yield/reliability tradeoffs and yield modeling of repairable memories is discussed. Yield learning based on correlation to defect inspection and physical failure analysis is highlighted. Improved RAM circuit design techniques for noise and SEU mitigation are discussed, together with an overview of ECC approaches.

Finally, future challenges in memory testing and reliability are highlighted.

Further information in:
http://www.date-conference.com/conference/tutorial-m10


Additional Information

Paolo Bernardi

TTEP Vice Chair (Program)
Politecnico di Torino, I
Tel.: +39 011 564 7183
Fax: +39 011 564 7099
Email: paolo.bernardi@polito.it

Committee

VICE CHAIR (PROGRAM)

  • P. BERNARDI – Politecnico di Torino

PAST CHAIR

  • D. GIZOPOULOS – University of Athens

FINANCE CHAIR

  • C.-H. CHIANG – Alcatel-Lucent

PUBLICITY CHAIRS

  • G. DI NATALE – LIRMM
  • E. SANCHEZ – Politecnico di Torino

PLANNING CHAIR

  • Y. ZORIAN – Synopsis

INDUSTRIAL RELATIONS CHAIR

  • R. GALIVANCHE – INTEL Corporation

AUDIO/VISUAL CHAIRS

  • S. MENON – INTEL Corporation
  • O. SINANOGLY – NYU in Abu-Dhabi

ELECTRONIC MEDIA CHAIRS

  • S. DI CARLO – Politecnico di Torino
  • A. BOSIO – LIRMM

ORGANIZING LIASONS

  • F. FUMMI – DATE'15
  • D. GIZOPOULOS – LATW'15
  • S. RAVI – VTS'15
  • Y. ZORIAN – ITC'15
  • Y. ZHANG – ATS'15

PROGRAM COMMITTEE
  • Robert C. Aitken – ARM, USA
  • Davide Appello – STMicroelectronics, I
  • Kanad Chakraborty – Lattice Semiconductor, USA
  • Sreejit Chakravarty – LSI logic, USA
  • Kun Young Chung – Samsung, USA
  • Scott Davidson – Oracle, USA
  • Anne E. Gattiker – IBM, USA
  • Kazumi Hatayama – NAIST, J
  • Doug Josephson – Intel Corporation, USA
  • Hans Manhaeve – Qstar, B
  • Amit Majumdar – Xilinx, USA
  • Erik Jan Marinissen – IMEC, B
  • Stephen Sunter – Mentor, USA
  • Baosheng Wang – AMD, USA

 

For more information, visit us on the web at: http://ttep.tttc-events.org/ttep/tutorials.html 

The Test Technology Educational Program 2015 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC)


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

PAST CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

TTTC 1ST VICE CHAIR
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

SECRETARY
Joan FIGUERAS
Un. Politec. de Catalunya - Spain
Tel. +34-93-401-6603
E-mail figueras@eel.upc.es

ITC GENERAL CHAIR
Gordon W. ROBERTS
McGill University
- Canada
Tel. +1-514-398-6029
E-mail gordon.roberts@mcgill.ca

TEST WEEK COORDINATOR
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

TUTORIALS AND EDUCATION
Paolo BERNARDI

Politecnico di Torino
- Italy
Tel. +39-011-564-7183
E-mail paolo.bernardi@polito.it

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Giorgio DI NATALE
LIRMM - France
Tel. +33-467-41-85-01
E-mail giorgio.dinatale@lirmm.fr

 

PRESIDENT OF BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com

SENIOR PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 2ND VICE CHAIR
Rohit KAPUR

Synopsys, Inc.
- USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
Krish CHAKRABARTY
Duke University - USA
Tel. +1
E-mail krish@ee.duke.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Patrick GIRARD
LIRMM - France
Tel.+33 467 418 629
E-mail patrick.girard@lirmm.fr

ASIA & PACIFIC
Kazumi HATAYAMA
NAIST - Japan
Tel.+81-743-72-5221
E-mail k-hatayama@is.naist.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Synopsys, Inc. - USA
Tel. +1-650-584-7120
E-mail Yervant.Zorian@synopsys.com